Seanano.org: Projects: CANPORT: Parport Physical Connection

The following is the matchup of pins from the PC's parallel port and the CANPORT's 82527 CAN controller chip.

Parallel Port          CANPORT 
phys.    logical         82527 
------------------------------ 
3        D1 (DATA1)       SCLK 
4        D2 (DATA2)       MOSI 
5        D3 (DATA3)        CS# 
6        D4 (DATA4)     RESET# 
10       S6 (STATUS6)     MISO

The 82527 is hardwired to serial interface mode and only the pins shown above are connected to the parallel port.

SCLK: serial clock, data is read on rising edge of SCLK and changed on falling edge
CS#: slave select, data can only be inputted or outputted to 82527 when this pin is asserted (low)
MOSI: master out slave in, data line to 82527. sampled once every pulse of SCLK
MISO: master in slave out, data line from 82527. sampled once every pulse of SCLK

To talk to the 82527, the CPU must first set CS# low. Then it must transmit an address byte followed by a serial control byte. To transmit a byte, the CPU must set the MOSI bit properly and then strobe SCLK. This must happen once per bit transferred. This is done for each data byte if it is a write command. If it is a read command, then the same thing is done except the CPU reads the MISO every pulse of SCLK. Once the read or write is complete the CPU should set CS# high.

Serial Control Byte ( - = reserved (set to 0))

| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 
|Dir| - | - | - |     SDLC      |

Dir: Serial Transmission Direction
- 0 - read
- 1 - write
SDLC: Serial Data Length Code
- Number of data bytes to be written/read.
- Must be from 1 to 15.

Last modified: 01/01/2012 @ 06:22 am